In developing high-k dielectrics for use as gate insulating layers, the most common type of such high-k dielectrics have been metal oxides. These metal oxides have a significant higher dielectric constant than the historic gate insulator of silicon oxide. In developing these metal oxides it has become a problem of doping the source/drain with implants through such metal oxides. Thus, implanting through these metal oxides has been difficult because the metal oxides absorb and impede the progress of the dopants that are being implanted. This can result in shallower source/drain regions, which is undesirable, and also in the PN junctions being less abrupt. The energy of the implant can be increased to achieve the desired depth of the source/drains but the abruptness of the PN junctions that are formed is still reduced. The disadvantage of PN junctions that are not abrupt is increased resistance of the doped region due to the larger areas of low concentration of doping and also higher current leakage. The higher current leakage may result from the depletion region extending further and enclosing more areas that have defects. Further, the metal oxide must ultimately be removed in order to make contact to the source/drains.
To overcome this disadvantage of implanting through a metal oxide, there have been attempts to remove the metal oxide prior to performing the source/drain implants. Removal of this metal oxide, however, has been very difficult to control. If the etch of the metal oxide continues for too long, the underlying interfacial oxide is removed and the underlying silicon is pitted. Thus there is a need to provide a technique for removing metal oxides that does not result in pitting this silicon substrate.